ECC-SV Generator A Python-based tool for automatically generating SEC-DED (Single Error Correction, Double Error Detection) encoder and decoder modules in SystemVerilog. Overview This tool generates Error Correction Code (ECC) modules that can: Detect up to 2 bit errors Correct single bit errors Support both Even Parity (EP) and Odd Parity (OP) configurations The generated modules are written in SystemVerilog and follow standard ECC encoding/decoding principles using Hamming codes with an additi...