GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation
Index
Index
Description
Area usage and maximal frequency
Dependencies
CPU generation
Regression tests
Interactive debug of the simulated CPU via GDB OpenOCD and Verilator
Using Eclipse to run and debug the software
By using gnu-mcu-eclipse
By using Zylin plugin (old)
Briey SoC
Murax SoC
Running Linux
Build the RISC-V GCC
CPU parametrization and instantiation example
Add a custom instruction to the CPU via the plugin system
Adding a new CSR via the plugin system
CPU clock and resets
VexRiscv Arch...
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