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Impact of Extremely Low Temperatures On The 5nm SRAM Array Size and Performance

A new technical paper titled “Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures” was published by researchers at University of Stuttgart, IIT Kanpur, National Yang Ming Chiao Tung University, Khalifa University, and TU Munich. Abstract “Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the ...

Read more at semiengineering.com

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