Part 4: QFTASM and Cogol Architecture Overview In short, our computer has a 16-bit asynchronous RISC Harvard architecture. When building a processor by hand, a RISC (reduced instruction set computer) architecture is practically a requirement. In our case, this means that the number of opcodes is small and, much more importantly, that all instructions are processed in a very similar manner. For reference, the Wireworld computer used a transport-triggered architecture, in which the only instructio...