2024-07-24 20:45 I teased at this a bit in my previous posts and finally have a setup I’m happy with, so I thought I’d do a more in-depth writeup. To recap, the planned architecture for most of my future large-scale embedded projects is a fairly large (AMD Xilinx Kintex-7 or Artix / Kintex UltraScale+) FPGA for the high speed data plane paired with a STM32H735 for the control plane with a memory mapped interface between them. Why a two-chip solution? This is somewhat reminiscent of SoC FPGAs lik...