Getting into way too much detail with the Z80 netlist simulation
TL;DR: a detailed look at Z80 instruction timings with the help of a
Z80 netlist simulation.
Table of Content
Table of Content
Intro
The shape of Z80 instructions
General Instruction Timing
M-cycles and T-states
Opcode Fetch Machine Cycles
Memory Read Machine Cycles
Memory Write Machine Cycles
IO Read and Write Machine Cycles
Wait states
Extra Clock Cycles
Overlapped Execution
The 3 Instruction Subsets
The 2-3-3 Opcode Bit Pattern
Main Instructions
Main Quadrant 1 (xx = 01)
Main Quadrant 2 (xx =...
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