Veryl is a modern hardware description language. This project is under the exploration phase of language design. If you have any idea, please open Issue. Document 日本語 PlayGround Documentation quick links Concepts Example Installation Usage License Contribution Concepts Veryl is designed as a "SystemVerilog Alternative". There are some design concepts. Simplified syntax Based on SystemVerilog / Rust Removed traditional Verilog syntax Transpiler to SystemVerilog Human readable SystemVerilog code g...