This article originally appeared in USENIX ;login: magazine, shepherded by Rik Farrow. As AI models grow larger and more complex, traditional computing architectures are hitting performance and efficiency limits. A new class of hardware, wafer-scale AI chips, pushes these boundaries by integrating hundreds of thousands of cores and massive on-chip memory onto a single wafer. Yet hardware alone is not enough: system software must evolve to fully harness its capabilities. This article examines how...