Designing a Low Latency 10G Ethernet Core - Part 1 (Introduction)
View the code on GitHub
Links to the other parts in this series:
Introduction (this post)
Design Overview and Verification
Low Latency Techniques
Performance Measurement and Comparison
Potential Improvements
This is the first in a series of blog posts describing my experience developing a low latency 10G Ethernet core for FPGA. I decided to do this as a personal project to develop expertise in low latency FPGA design and high-speed Ethernet, as well as to experiment with tools and techniques tha...
Read more at ttchisholm.github.io